1. Field of the Invention
The present invention relates to a substrate, and more particularly to a multi model glass (MMG) type substrate and a method of fabricating the same.
2. Discussion of the Related Art
Flat panel display (FPD) devices having light weight, thin profile, and low power consumption characteristics are being developed. Liquid crystal display (LCD) devices may be categorized as non-emissive display devices and are commonly used in notebook and desktop computers because of their high resolution, capability of displaying colored images, and high quality image display.
The LCD panel includes two substrates facing and spaced apart from each other. A liquid crystal material is interposed between the two substrates. Liquid crystal molecules of the liquid crystal material have a dielectric constant and refractive index anisotropic characteristics due to their long, thin shape. In addition, two electric field generating electrodes are formed on the two substrates, respectively. Accordingly, an orientation alignment of the liquid crystal molecules can be controlled by supplying a voltage to the two electrodes. Transmittance of the LCD panel is thus changed according to polarization properties of the liquid crystal material.
An active matrix (AM) LCD including a thin film transistor as a switching device and a pixel electrode connected to the thin film transistor has recently been developed. The thin film transistor and the pixel electrode are arranged in a matrix. The AM LCD has been given the most attention of the flat panel displays because the AM LCD has a good resolution and an ability to display a moving picture.
FIG. 1 is a schematic perspective view of an LCD device according to the related art.
As shown in FIG. 1, an LCD device 1 includes an upper substrate 5, a lower substrate 21 facing the upper substrate 5, and a liquid crystal layer 40 interposed between the upper and lower substrates 5 and 21. A color filter layer 10 is formed on the upper substrate 5, a black matrix 7 is formed on the color filter layer 10, and a common electrode 15 is formed on the black matrix 7. Color filter layer 10 includes red (R), green (G) and blue (B) color filter elements.
A gate line 24 and a data line 30 crossing the gate line 24 define a pixel region P. The gate line 24 and the data line 30 are formed on the lower substrate 21. A thin film transistor Tr is disposed near a crossing of the gate and data lines 24 and 30, and a pixel electrode 35 is connected to the thin film transistor Tr in the pixel region P.
In addition, the LCD device 1 includes a gate pad electrode 25 connected to the gate line 24 and a data pad electrode 35 connected to the data line 30. The gate pad electrode 25 and the data pad electrode 35 are disposed in a gate pad region GPA and a data pad region DPA in a periphery region of an active region AA, respectively. Furthermore, a printed circuit board (PCB) may be connected to the gate and the data pad electrodes 25 and 35 in the gate and the data pad regions GPA and DPA. The LCD device 1 may further include a backlight unit having a plurality of optical sheets and a lamp (not shown).
A fabricating method of the LCD device 1 includes forming an array element including the thin film transistor Tr and the pixel electrode 35 connected to the thin film transistor Tr on the upper substrate 5, forming a color filter element including the black matrix 7, the color filter layer 10 and the common electrode 15 on the lower substrate 21, attaching the upper and the lower substrates 5 and 21, and interposing the liquid crystal layer 40 between the upper and the lower substrates 5 and 21.
A first substrate including a plurality of array cells is prepared and a second substrate including a plurality of color filter cells is prepared. In the attaching process, each of the array cells and each of the color filter cells face each other, and one of the array cell and one of the color filter cell have a seal pattern. The attached first and second substrates may be referred as a mother panel. The mother panel is scribed by cells. Accordingly, the interposing process is performed with respect to respective cells and the LCD panel is completed by sealing an opening portion of the seal pattern of each of the cells.
To increase the utility of the substrates, cells having various sizes may be included in the substrate. A main model cell having a relative big size in a main region and a sub model cell having a relative small size in a periphery region of the main region may be utilized for cellular phones or Personal Digital Assistants (PDA). The main model cell and the sub model cell are defined on the substrates to thereby increase productivity. The periphery region may be considered a dummy region in view of the main region, and the sub model cell is defined in the periphery region. Therefore, the utility of the substrates can be increased compared to the utility of the related art.
The substrate having the various size cells may be referred to as a multi model glass (MMG) type substrate, wherein the main model cell includes a gate line, a gate link line and a gate pad electrode. The gate line, the gate link line, and the gate pad electrode may be formed of aluminum (Al). The sub model cell includes a gate line, a gate link line and a gate pad electrode formed of a same material as that of the gate line, the gate link line, and the gate pad electrode of the main model cell.
However, when a gate pattern including a gate line, a gate link line and a gate pad electrode is formed to include the same materials in both the main model cell and the sub model cell, the gate pattern in the main model cell is performed by a module process within a short period of time. Therefore, corrosion does not occur in the main model cell because the gate pad electrode is not exposed under atmosphere within a short period of time. However, the gate pad electrode of the sub model cell is exposed for a long period of time under atmosphere because it is delivered in a panel state before performing the module process. As a result, corrosion severely occurs in the sub model cell. Corrosion occurs in the gate pad region between the gate pad electrode and a gate pad electrode terminal. The gate pad electrode terminal may be formed of ITO.